Publications and patents on Trench-SOI and Integrated High Voltage Devices
If you are interested in this topic the following papers on the topics of
- Deep Trench Isolation (DTI) and Silicon On Insulator (SOI)
- Integrated power devices
might be useful to dig into it in more detail.
R. Lerner and N. H. Hansen, “Commercial Sweet Spots for GaN and CMOS Integration by Micro-Transfer-Printing”, Proceedings 15th International Seminar On Power Semiconductors, Prague, Aug 26-27 2021, 99-106
Ralf Lerner, “Integration of GaN and CMOS logic”, GaN summer school on wide-bandgap devices, July 8-11 2019 in Ghent, Belgium
R. Lerner; K. Heinrich; M. Erstling, P. Kornetzky, „Thick Copper Re-Distribution Layer for Integrated High Voltage Transistors“, Proceedings 14th International Seminar On Power Semiconductors, Prague, Aug 29-31, 2018, 70-76
R. Lerner, S. Eisenbrandt, F. Fischer, A. Fecioru, A. J. Trindade, S. Bonafede, C. Bower, P. Waltereit, R. Reiner, H. Czap, “Flexible and scalable heterogeneous integration of GaN HEMTs on Si CMOS by micro Transfer Printing”, Physica status solidi. A 215 (2018), Nr.8
Stefan Eisenbrandt and Ralf Lerner, "Printing GaN HEMTs onto silicon CMOS", Compound Semiconductor Magazine, January/February 2018
Ralf Lerner, Stefan Eisenbrandt; "Thermal investigations of heterogeneously integrated GaN HEMTs on Si-CMOS by micro-Transfer-Printing"; Compound Semiconductor Week, Berlin, 2017
Ralf Lerner, Stefan Eisenbrandt, Frank Fischer, Christopher Bower, Patrick Waltereit, Richard Reiner, Heiko Czap; "Flexible and scalable heterogeneous integration of GaN HEMTs on Si-CMOS by micro-Transfer-Printing"; Compound Semiconductor Week, Berlin, 2017
Ralf Lerner; Andreas Käberlein, Marco Ramsbeck; Daniel Beyer, Heiko Berger; Rocco Holzhey, Ulrich Büttner, Andreas Schrön; Johannes Zimmet, Michael Volk, „Alternative level shifting devices for 900V gate drivers “, 13th International Seminar on Power Semiconductors, ISPS, Prague, Czech Republic, 2016
Ralf Lerner, Stefan Eisenbrandt, Christopher Bower, Salvatore Bonafede & Alin Fecioru, Richard Reiner, Patrick Waltereit; „Integration of GaN HEMTs onto Silicon CMOS by Micro Transfer Printing“, Proceedings of the 28th International Symposium on Power Semiconductor Devices and ICs, Prague, June 2016, 451-454
Ralf Lerner, Stefan Eisenbrandt, Salvatore Bonafede, Matthew A. Meitl, Alin Fecioru, António Jose Trindade, Richard Reiner, Patrick Waltereit, Christopher A. Bower, “Heterogeneous Integration of Microscale Gallium Nitride Transistors by Micro-Transfer-Printing”, Proceedings of the 66th Electronic Components and Technology Conference, ECTC, Las Vegas, 2016, 1186-1189
Ralf Lerner, Klaus Schottmann, Siegfried Hering, Andreas Käberlein, Matthias Fritzsch, Klaus Schneider, Daniel Beyer, Steffen Heinz, "Comparison of different Device Concepts to increase the Operating Voltage of a Trench Isolated SOI Technology to above 900V" ,Facta Universitatis, Series: Electronics and Energetics Vol 28, No 4 (2015), (645-656)
Ralf Lerner, Klaus Schottmann, Siegfried Hering, Andreas Käberlein, Matthias Fritzsch, Klaus Schneider, Daniel Beyer, Steffen Heinz, "Using SOI capabilities to increase breakdown voltages from < 600V to >900V", ISPS 2014, Prague, Czech Republic, August 27-29, 2014
R. Lerner; D. Gaebler, K. Schottmann and S. Hering, "A Trench Isolated Thick SOI Process as Platform for Various Electrical and Optical Integrated Devices", IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, Monterey, California, October 07-10, 2013 .
Ralf Lerner; Klaus Schottmann; Siegfried Hering; Daniel Gaebler, "Trench Isolated Thick SOI Process for Various Optical and High VoltageDevices", 2013 International Semiconductor Conference Dresden-Grenoble (ISCDG), September 26-27, 2013, Dresden
Ralf Lerner, Klaus Schottmann, Gabriel Kittler; "Device Engineering for a Modular 650 V Transistor Assortment", Semiconductor Conference Dresden 2011, September 27 to 28, 2011
G. Kittler, R. Lerner, U. Eckoldt; "Final Report of the funded project "SparTip - OPTI-TETRIS", Documentation for the Technical Information Library Hannover
Ralf Lerner, Gabriel Kittler, Klaus Schottmann; "Modular650V SOI Process with Various High Voltage Transistors", PCIM Europe 2011, May 17-19 2011, Nuremberg, Germany
G. Kittler, R. Lerner, U. Eckoldt, K. Schottmann, M. Fritzsch, M. Schramm, K. Erler, S. Heinz, J. T. Horstmann, “SingleTrench Isolation for a 650 V SOI Technology with Low MechanicalStress”, IEEE International SOI Conference, 11-14 October, 2010, San Diego
R. Lerner, G. Kittler, U. Eckoldt, K. Schottmann et al.; “Optimization of Trench Manufacturing for a new High-Voltage Semiconductor Technology”, IEEE International Symposium on Industrial Electronics, 4-7 July 2010,Bari
R. Lerner; U. Eckoldt; K. Schottmann; G. Kittler; “Smart Power Anwendungen realisiert durch Trench-Isolationsprozesse“, BMBF Conference "SME-Innovative" in Darmstadt, Germany, November17-18 2008
R. Lerner; U. Eckoldt; K. Schottmann; “Time Dependent Isolation Capability of High Voltage Deep Trench Isolation“, 20th International Symposium on Power Semiconductor Devices & ICs, Orlando, Florida May 18-22, 2008
A. Lange, S. Heinz; K. Erler; G. Ebest; R. Lerner; U. Eckoldt; K. Schottmann; “Modelling the Leakage Current of Dielectric Isolation Structures in a High-Voltage Semiconductor Technology”, International Symposium on Industrial Electronics 2007 Vigo, Spain, June 4-7
R. Lerner; J. Carlson; “Trench Enclosed MOS Transistors for High Voltage Smart Power ICs“, IEEE EDS Workshop on Advanced Electron Devices, June, 14th 2006
P. Igic; P. Holland; S. Batcup; R. Lerner; A. Menz; “Technology forPower Integrated Circuits with Multiple Vertical Power Devices“, International Symposium on Power Semiconductor Devices & ICs, ISPSD 2006 Naples, ITALY, June 4th-8th, 2006
R. Lerner; U. Eckoldt; A. Hölke; A. Nevin; G. Stoll; “Optimized Deep Trench Isolation for High Voltage Smart Power Process“, International Symposium on Power Semiconductor Devices & ICs, ISPSD, Santa Barbara, May 05;
R. Lerner; U. Eckoldt; J. Knopke; “HighVoltage Smart Power Technology with Dielectric Insulation“, Conference on Integrated Power Systems 2002
M. Netzel; R. Lerner; R. Siemieniec; J. Lutz; “PT-IGBT and Freewheeling Diode for 3.3kV using Lifetime Control Techniques and Low Efficiency Emitters“, FACTA UNIVERSITATIS (NIS) Ser.: Elec. Energ.vol. 15. No. 1
Granted Patents on these topics
Ralf Lerner; DE 10120383 B4; Verfahren zur Metallisierung von Siliziumscheiben durch Aufsputtern
Ralf Lerner; DE 10154658 B4; Integrierter Leistungsschaltkreis mit verbessertem elektrischen und thermischen Durchgangswiderstand und Verfahren zu seiner Herstellung
Ralf Lerner, Dr. Uwe Eckoldt; DE 10246949 B4; Verbesserte Trench-Isolation und Herstellungsverfahren
Ralf Lerner, Dr. Uwe Eckoldt; US 7271074 B2; Trench Insulating in Substrate Disks comprising Logic Semiconductors and Power Semiconductors
Ralf Lerner; DE 10317747 B3; Verfahren zur Kontrolle des Dickenabtrags von gebondeten Halbleiterscheibenpaaren
Ralf Lerner, Dr. Uwe Eckoldt; DE 102004048626 B3; Oxidationsverfahren von Siliziumscheiben zur Reduzierung von mechanischen Spannungen
Ralf Lerner; US 7588948 B2; Test Structure For Electrically Verifying The Depths Of Trench-Etching In An SOI Wafer, And Associated Working Methods
Ralf Lerner; US 7598098 B2; Monitoring The Reduction In Thickness As Material Is Removed From A Wafer Composite And Test Structure For Monitoring Removal Of Material
Ralf Lerner; DE 10317748 B4; Verfahren zur Überprüfung von Isoliergrabenätzungen in SOI-Scheiben mittels einer Teststruktur
Ralf Lerner, Dr. Gunter Stoll, Klaus Schottmann; DE 10343132 B4; Isolierte MOS-Transistoren mit ausgedehntem Drain-Gebiet für erhöhte Spannungen
Ralf Lerner, Dr. Uwe Eckold; US 7625805 B2; Passivation of deep isolating separating trenches with sunk covering layers
Ralf Lerner, Dr. Uwe Eckoldt, Thomas Oetzel; DE 102004017073 B4; Creation Of Dielectrically Insulating Soi-Technological Trenches Comprising Rounded Edges For Allowing Higher Voltages
Ralf Lerner; DE 20320829 U1; Isolationsgraben (Trench) mit unterschiedlichen Dotierungen der Seitenwände
Ralf Lerner; US 7989921 B2; SOI vertical bipolar power component
Ralf Lerner; DE 10 2004 028 474 B4; Integriertes Bauelement in einer SOI-Scheibe
Ralf Lerner, Wolfgang Miesch; US 8190415 B2; Method for the construction of vertical power transistors with differing powers by combination of pre-defined part pieces
Ralf Lerner, Dr. Uwe Eckoldt; US 7517813 B2; Two-step oxidation process for semiconductor wafers
Ralf Lerner, Wolfgang Miesch; DE 102004048278 B3; Simulations- und/oder Layoutverfahren für Leistungstransistoren, die für unterschiedliche Leistungen ausgelegt sind
Ralf Lerner; DE 102005010944 B5; Verfahren zur Herstellung eines Trägerscheibenkontaktes in integrierten Schaltungen mit Hochspannungsbauelementen auf der Basis der SOI-Technologie und integrierte Schaltungen mit entsprechenden Grabenstrukturen
Ralf Lerner, Dr. Uwe Eckold; EP 1709677 B1; Passivation of deep isolating separating trenches with sunk covering layers
Ralf Lerner; DE 20122577 U1; VDMOS-Transistor
Ralf Lerner, Dr. Uwe Eckoldt; DE 102005059034 B4; SOI-Isolationsgrabenstrukturen
Ralf Lerner, Dr. Uwe Eckoldt; DE 102005059035 B4; Isolationsgrabenstrukturen für hohe Spannungen
Ralf Lerner; EP 1910952 B1; Method For Designing A Mask For An Integrated Circuit Having Separate Testing Of Design Rules For Different Regions Of A Mask Plane
Ralf Lerner;DE 102007035251 B3;Verfahren zur Herstellung von Isolationsgräben mit unterschiedlichen Seitenwanddotierungen
Ralf Lerner, Dr. Uwe Eckoldt, Thomas Oetzel; US 7989308 B2;Creation Of Dielectrically Insulating Soi-Technological Trenches Comprising Rounded Edges For Allowing Higher Voltages
Ralf Lerner; US 8053897 B2; Production Of A Carrier Wafer Contact In SOI Trench Insulated Integrated Circuits Provided With A High-Voltage Components
Ralf Lerner; US 8247884 B2; Semiconductor Structure for the Production of a carrier wafer contact in a Trench-Insulated SOI Disk
Ralf Lerner, Wolfgang Miesch; US 8448101 B2; Layout Method For Vertical Power Transistors Having A Variable Channel Width
Ralf Lerner, Dr. Uwe Eckoldt; DE 102008029235 B3; Kreuzungen von Isolationsgräben der SOI-Technologie
Ralf Lerner; DE 102008028452 B4; Leistungstransistor für hohe Spannungen in SOI-Technologien
Ralf Lerner; US 2011/0143519 A1; Production Of Isolation Trenches With Different Sidewall Dopings
Ralf Lerner; US 8823095 B2; MOS-Power Transistors With Edge Termination With Small Area Requirement
Ralf Lerner, Gabriel Kittler; DE 102009051521 B4; Herstellung von Siliziumhalbleiterscheiben mit III-V-Schichtstrukturen für High Electron Mobility Transistoren (HEMT) und eine entsprechende Halbleiterschicht anordnung
Ralf Lerner, Gabriel Kittler; US 8759169 B2; Method for producing Silicon Semiconductor Wafers comprising a layer for integrating III-V Semiconductor Components
Ralf Lerner, Gabriel Kittler, Astrid Küffner; DE 102010035296 B4; Randabschlussstruktur für Transistoren mit hohen Durchbruchspannungen (Randabschlussstruktur für integrierte Hochvolttransistoren mit Metallüberführungen)
Ralf Lerner, Dr. Uwe Eckoldt; US 8530999 B2; Semiconductor Component with Isolation Trench Intersections
Ralf Lerner, Gabriel Kittler; US 2012/0223367; Method for fabricating semiconductor wafers for the integration of silicon components with HEMTs, and appropriate semiconductor layer arrangement
Ralf Lerner, Wolfgang Miesch; US 8793116 B2; Method for the construction of vertical power transistors with differing powers by combination of pre-defined part pieces
Ralf Lerner; DE 102012018013 B4; Spiralförmige, integrierbare Spulen mit zentrischen Anschlüssen in planarer grabenisolierter Siliziumhalbleitertechnologie
(Integrierte planare Spulen mit Substratstromzuführung)